Simple, elementary, pre-defined subblocks to easily model common SoC blocks.

Test program interface drivers for the Origen tester standard library

Helpers to consume and generate test IP in STIL format (IEEE 1450)

Origen plugin to render JTAG-based patterns in Serial Vector Format (SVF)

Driver for single-wire-debug interface.

Deals with the trials and tribulations of updating Origen within a corporate Linux env

A parser and generator for Verilog (IEEE 1364)

Origen plugin to assign and track test program bins and test numbers